• System on Chip (SoC) - Bus Architectures

      Title: System on Chip (SoC) - Bus Architectures

      Topic: Digital System Design

      Category Level: Problem solving

      Degree weight: 4

      Materials: RS-232, LEDs, Input switches, VHDL, Xilinx ISE, Xilinx Isim

      Augmented Reality Interface: Y

      Remote Lab: Y

      Short description: In the previous exercise (DSD_21_ UART Core Implementation on E2LP Base Board platform) a UART controller was developed as an example of a more complex digital system. However, a single module cannot achieve most functionalities required from modern embedded computer systems. FPGA technology enables development and integration of different modules on a single chip to create a complex highly coherent complex system with significant performance improvement - System on a Chip (SoC). A SoC does not necessarily need to include a microprocessor, but in most cases it does to provide increased flexibility. The core of SoC development is connecting processing elements with each other and with peripherals in a fast and efficient manner. Components are usually interconnected with different types of busses. While there is a variety of different bus architectures and interfaces, AXI interface (part of ARM family AMBA specification) is the most prominent one and will be in the focus of this exercise. This exercise will also include introduction to working with more advance Xilinx tools targeting SoC design. The final goal of this exercise is to develop a SoC which will integrate microprocessor, set of basic peripherals and a UART controller developed in the previous exercise.

    UART Core Implementation on E2LP Base Board platformDigital Filters - FIR Filter